Investigation of stress induced interface states in Al2O3/InGaAs metal-oxide-semiconductor capacitors

F. Palumbo; R. Winter; K. Tang; P. C. McIntyre; M. Eizenberg

doi:10.1063/1.4982912

Investigation of stress induced interface states in Al₂O₃/InGaAs metal-oxide-semiconductor capacitors

F. Palumbo, R. Winter, K. Tang, P. C. McIntyre, M. Eizenberg

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

Implementation of high-k dielectrics on InGaAs for CMOS technology requires capabilities to predict long-time degradation and the impact of process changes on degradation processes. In this work, the degradation under constant voltage stress of metal gate/Al₂O₃/InGaAs stacks is studied for n-type and p-type As₂ passivated InGaAs substrates. The results show that the degradation for both positive bias and negative bias did not produce Al₂O₃ oxide traps, while the distribution of interface states increased. In particular, the distribution of interface states, calculated by the distributed impedance equivalent circuit model, increased significantly after positive bias stress regardless of the doping type of the substrate. The injection of carriers from the semiconductor conduction band into the gate dielectric enhanced the generation of interface states but not the generation of oxide traps, suggesting that the interfacial degradation is related primarily to the InGaAs surface and not to the oxide layer.

Original language	English
Article number	174105
Journal	Journal of Applied Physics
Volume	121
Issue number	17
DOIs	https://doi.org/10.1063/1.4982912
State	Published - 7 May 2017
Externally published	Yes

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@article{9fa0e13746c54dd5862957e114022404,

title = "Investigation of stress induced interface states in Al2O3/InGaAs metal-oxide-semiconductor capacitors",

abstract = "Implementation of high-k dielectrics on InGaAs for CMOS technology requires capabilities to predict long-time degradation and the impact of process changes on degradation processes. In this work, the degradation under constant voltage stress of metal gate/Al2O3/InGaAs stacks is studied for n-type and p-type As2 passivated InGaAs substrates. The results show that the degradation for both positive bias and negative bias did not produce Al2O3 oxide traps, while the distribution of interface states increased. In particular, the distribution of interface states, calculated by the distributed impedance equivalent circuit model, increased significantly after positive bias stress regardless of the doping type of the substrate. The injection of carriers from the semiconductor conduction band into the gate dielectric enhanced the generation of interface states but not the generation of oxide traps, suggesting that the interfacial degradation is related primarily to the InGaAs surface and not to the oxide layer.",

author = "F. Palumbo and R. Winter and K. Tang and McIntyre, {P. C.} and M. Eizenberg",

note = "Publisher Copyright: {\textcopyright} 2017 Author(s).",

year = "2017",

month = may,

day = "7",

doi = "10.1063/1.4982912",

language = "英语",

volume = "121",

journal = "Journal of Applied Physics",

issn = "0021-8979",

publisher = "American Institute of Physics",

number = "17",

}

TY - JOUR

T1 - Investigation of stress induced interface states in Al2O3/InGaAs metal-oxide-semiconductor capacitors

AU - Palumbo, F.

AU - Winter, R.

AU - Tang, K.

AU - McIntyre, P. C.

AU - Eizenberg, M.

PY - 2017/5/7

Y1 - 2017/5/7

N2 - Implementation of high-k dielectrics on InGaAs for CMOS technology requires capabilities to predict long-time degradation and the impact of process changes on degradation processes. In this work, the degradation under constant voltage stress of metal gate/Al2O3/InGaAs stacks is studied for n-type and p-type As2 passivated InGaAs substrates. The results show that the degradation for both positive bias and negative bias did not produce Al2O3 oxide traps, while the distribution of interface states increased. In particular, the distribution of interface states, calculated by the distributed impedance equivalent circuit model, increased significantly after positive bias stress regardless of the doping type of the substrate. The injection of carriers from the semiconductor conduction band into the gate dielectric enhanced the generation of interface states but not the generation of oxide traps, suggesting that the interfacial degradation is related primarily to the InGaAs surface and not to the oxide layer.

AB - Implementation of high-k dielectrics on InGaAs for CMOS technology requires capabilities to predict long-time degradation and the impact of process changes on degradation processes. In this work, the degradation under constant voltage stress of metal gate/Al2O3/InGaAs stacks is studied for n-type and p-type As2 passivated InGaAs substrates. The results show that the degradation for both positive bias and negative bias did not produce Al2O3 oxide traps, while the distribution of interface states increased. In particular, the distribution of interface states, calculated by the distributed impedance equivalent circuit model, increased significantly after positive bias stress regardless of the doping type of the substrate. The injection of carriers from the semiconductor conduction band into the gate dielectric enhanced the generation of interface states but not the generation of oxide traps, suggesting that the interfacial degradation is related primarily to the InGaAs surface and not to the oxide layer.

UR - http://www.scopus.com/inward/record.url?scp=85019023668&partnerID=8YFLogxK

U2 - 10.1063/1.4982912

DO - 10.1063/1.4982912

M3 - 文章

AN - SCOPUS:85019023668

SN - 0021-8979

VL - 121

JO - Journal of Applied Physics

JF - Journal of Applied Physics

IS - 17

M1 - 174105

ER -

Investigation of stress induced interface states in Al₂O₃/InGaAs metal-oxide-semiconductor capacitors

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