Physical mechanism of progressive breakdown in gate oxides

TY - JOUR

T1 - Physical mechanism of progressive breakdown in gate oxides

AU - Palumbo, Felix

AU - Lombardo, Salvatore

AU - Eizenberg, Moshe

PY - 2014/6/14

Y1 - 2014/6/14

N2 - The definition of the basic physical mechanisms of the dielectric breakdown (BD) phenomenon is still an open area of research. In particular, in advanced complementary metal-oxide-semiconductor (CMOS) circuits, the BD of gate dielectrics occurs in the regime of relatively low voltage and very high electric field; this is of enormous technological importance, and thus widely investigated but still not well understood. Such BD is characterized by a gradual, progressive growth of the gate leakage through a localized BD spot. In this paper, we report for the first time experimental data and a model which provide understanding of the main physical mechanism responsible for the progressive BD growth. We demonstrate the ability to control the breakdown growth rate of a number of gate dielectrics and provide a physical model of the observed behavior, allowing to considerably improve the reliability margins of CMOS circuits by choosing a correct combination of voltage, thickness, and thermal conductivity of the gate dielectric.

AB - The definition of the basic physical mechanisms of the dielectric breakdown (BD) phenomenon is still an open area of research. In particular, in advanced complementary metal-oxide-semiconductor (CMOS) circuits, the BD of gate dielectrics occurs in the regime of relatively low voltage and very high electric field; this is of enormous technological importance, and thus widely investigated but still not well understood. Such BD is characterized by a gradual, progressive growth of the gate leakage through a localized BD spot. In this paper, we report for the first time experimental data and a model which provide understanding of the main physical mechanism responsible for the progressive BD growth. We demonstrate the ability to control the breakdown growth rate of a number of gate dielectrics and provide a physical model of the observed behavior, allowing to considerably improve the reliability margins of CMOS circuits by choosing a correct combination of voltage, thickness, and thermal conductivity of the gate dielectric.

UR - http://www.scopus.com/inward/record.url?scp=84902436885&partnerID=8YFLogxK

U2 - 10.1063/1.4882116

DO - 10.1063/1.4882116

M3 - 文章

AN - SCOPUS:84902436885

SN - 0021-8979

VL - 115

JO - Journal of Applied Physics

JF - Journal of Applied Physics

IS - 22

M1 - 224101

ER -