Characteristics of stress-induced defects under positive bias in high-k/InGaAs stacks

F. Palumbo; R. Winter; I. Krylov; M. Eizenberg

doi:10.1063/1.4885535

Characteristics of stress-induced defects under positive bias in high-k/InGaAs stacks

F. Palumbo^*, R. Winter, I. Krylov, M. Eizenberg

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

The introduction of InGaAs as a channel material for complementary metal-oxide-semiconductor technology presents major challenges in terms of the characterization of the various defects that affect the performance and reliability. Understanding the generation of defects by constant voltage stresses is crucial in terms of their concentration profiles and energy levels. In particular, we want to understand the real nature of the defects responsible for the dispersion of C-V in strong accumulation. Here, we show that the degradation under positive bias of metal/ANOj/n-InGaAs capacitors reveals two contributions depending on the temperature that affects the C-V curves in a different way. Based on features of stressed C-V curves, it is possible to estimate the onset point of the distribution of border traps near the midgap condition. The results suggest that these defects are strongly related to the characteristics of the InGaAs substrate.

Original language	English
Article number	252907
Journal	Applied Physics Letters
Volume	104
Issue number	25
DOIs	https://doi.org/10.1063/1.4885535
State	Published - 23 Jun 2014
Externally published	Yes

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title = "Characteristics of stress-induced defects under positive bias in high-k/InGaAs stacks",

abstract = "The introduction of InGaAs as a channel material for complementary metal-oxide-semiconductor technology presents major challenges in terms of the characterization of the various defects that affect the performance and reliability. Understanding the generation of defects by constant voltage stresses is crucial in terms of their concentration profiles and energy levels. In particular, we want to understand the real nature of the defects responsible for the dispersion of C-V in strong accumulation. Here, we show that the degradation under positive bias of metal/ANOj/n-InGaAs capacitors reveals two contributions depending on the temperature that affects the C-V curves in a different way. Based on features of stressed C-V curves, it is possible to estimate the onset point of the distribution of border traps near the midgap condition. The results suggest that these defects are strongly related to the characteristics of the InGaAs substrate.",

author = "F. Palumbo and R. Winter and I. Krylov and M. Eizenberg",

note = "Publisher Copyright: {\textcopyright}2014 AIP Publishing LLC.",

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T1 - Characteristics of stress-induced defects under positive bias in high-k/InGaAs stacks

AU - Palumbo, F.

AU - Winter, R.

AU - Krylov, I.

AU - Eizenberg, M.

PY - 2014/6/23

Y1 - 2014/6/23

N2 - The introduction of InGaAs as a channel material for complementary metal-oxide-semiconductor technology presents major challenges in terms of the characterization of the various defects that affect the performance and reliability. Understanding the generation of defects by constant voltage stresses is crucial in terms of their concentration profiles and energy levels. In particular, we want to understand the real nature of the defects responsible for the dispersion of C-V in strong accumulation. Here, we show that the degradation under positive bias of metal/ANOj/n-InGaAs capacitors reveals two contributions depending on the temperature that affects the C-V curves in a different way. Based on features of stressed C-V curves, it is possible to estimate the onset point of the distribution of border traps near the midgap condition. The results suggest that these defects are strongly related to the characteristics of the InGaAs substrate.

AB - The introduction of InGaAs as a channel material for complementary metal-oxide-semiconductor technology presents major challenges in terms of the characterization of the various defects that affect the performance and reliability. Understanding the generation of defects by constant voltage stresses is crucial in terms of their concentration profiles and energy levels. In particular, we want to understand the real nature of the defects responsible for the dispersion of C-V in strong accumulation. Here, we show that the degradation under positive bias of metal/ANOj/n-InGaAs capacitors reveals two contributions depending on the temperature that affects the C-V curves in a different way. Based on features of stressed C-V curves, it is possible to estimate the onset point of the distribution of border traps near the midgap condition. The results suggest that these defects are strongly related to the characteristics of the InGaAs substrate.

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Characteristics of stress-induced defects under positive bias in high-k/InGaAs stacks

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