The electrical properties of a thin (350 Å) layer deposited on a molecular beam epitaxial grown Si0.89Ge0.11/Si(001) heterostructure and subsequently annealed at Ta = 550-800 °C were studied in a wide (80-325 K) temperature range. Annealing at 800 °C produces a single reaction product, the C54 phase of Ti(SiGe)2, while lower temperature anneals result in the coexistence of a few intermetallic compounds. It was found that while for annealing temperatures lower than 800 °C, the Fermi level is pinned with respect to the conduction band, annealing at 800 °C results in Fermi level partial pinning with respect to the valence band. The current flow in this case is controlled mainly by thermionic emission in the presence of interface states. Two kinds of traps were observed by deep level transient spectroscopy in the barrier region after the 800 °C annealing. Acceptor-like traps with an activation energy of ≈=0.46-0.5 eV, a capture cross-section σa= 1.3×10-12 cm2, and a density Dt≈ 3×1013 eV-1cm-2, which most likely originate from the strain relaxation in the SiGe epilayer, were found to be responsible for the partial Fermi level pinning at the interface. Electron traps with an activation energy of ≈=0.17 eV and a capture cross-section σd=7.7×10-16 cm2 were also identified and attributed to the SiGe epilayer; they are assumed to originate from a well-known vacancy-oxygen center.