Characteristics of stress-induced defects under positive bias in high-k/InGaAs stacks

F. Palumbo*, R. Winter, I. Krylov, M. Eizenberg

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

The introduction of InGaAs as a channel material for complementary metal-oxide-semiconductor technology presents major challenges in terms of the characterization of the various defects that affect the performance and reliability. Understanding the generation of defects by constant voltage stresses is crucial in terms of their concentration profiles and energy levels. In particular, we want to understand the real nature of the defects responsible for the dispersion of C-V in strong accumulation. Here, we show that the degradation under positive bias of metal/ANOj/n-InGaAs capacitors reveals two contributions depending on the temperature that affects the C-V curves in a different way. Based on features of stressed C-V curves, it is possible to estimate the onset point of the distribution of border traps near the midgap condition. The results suggest that these defects are strongly related to the characteristics of the InGaAs substrate.

Original languageEnglish
Article number252907
JournalApplied Physics Letters
Volume104
Issue number25
DOIs
StatePublished - 23 Jun 2014
Externally publishedYes

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